Memory devices, including semiconductor memories such as static random access memories (SRAMs), can typically include a large number of circuit elements, e.g., transistors, formed in or above a substrate. In operation, such memory devices can typically output data and input data at relatively high speeds. When operating synchronously (i.e., according to timing based on a provided clock signal), the output and/or input of data can be timed relative to a timing signal. In such cases, there may be a “set-up” time during which data is valid prior to a clock edge, as well as a “hold-time” during which data is valid after such a clock edge. This presents a “data valid window” during which a data access can be valid.
As memory devices operate at higher and higher clock speeds, it can be more difficult to ensure a sufficient data valid window. Having a large enough data window is important for reliable operation of a memory interface in a system. To illustrate this, a conventional semiconductor memory device will now be described.
Referring now to FIG. 8, a conventional memory is shown in a block schematic diagram, and designated by the general reference character 800. A conventional memory device 800 can typically include an array of memory cells 802, address decoding circuitry for selecting memory cells for reading or writing data, and sensing circuitry for detecting or reading the content or data stored in the selected cells (not shown).
A memory device 800 can also include input/output (I/O) circuitry, including an I/O buffer 804 and an I/O driver 806. While FIG. 8 shows I/O circuitry for sending data from the memory device 800, one skilled in the art would recognize that such circuitry can also receive data for the memory device 800. Such conventional I/O circuitry can drive output data and/or latch input data according to a “valid window” specification.
A conventional memory 800 typically operates in conjunction with a memory controller. One such conventional arrangement is shown in FIG. 9. FIG. 9 is a block schematic diagram of a conventional memory system designated by the general reference character 900. A conventional memory system 900 can include a memory controller 902 and a memory device 904, which in this example is an SRAM. A memory controller 902 can control the memory device 904 by providing commands that enable various operations, including but not limited to read and write operations. Such command can be issued and/or latched on the edge of a system clock CLK.
As will be recalled, accessing a memory device 904 can require capturing data from an I/O driver during a particular time period (e.g., data valid window (DVW)) that is determined in relative to a timing signal. In the conventional example of FIG. 9, a timing signal can be clock signal CLK used by both a memory device 904 sending/receiving data, as well as a device requesting/sending data to a memory device 904. In the event data is captured outside of a DVW, the data accessed may be erroneous.
While memory devices may provide a particular response under ideal conditions, many times external factors, such as temperature drifts or other fluctuations in the operating conditions of a controller and/or memory device, can affect the operation of a memory system 900. In particular, a speed of a memory device 904 can be affected. Consequently, the time at which a DVW begins and the duration of the DVM can be adversely affected due to variations in operating conditions (e.g., process variations, ambient temperature, operating voltage or “PVT”).
To assist in synchronizing operations between devices, a conventional memory system 900 can often include some sort of synchronization circuit that utilizes a feedback signal between a memory controller 902 and memory device 904, such as a delay locked loop or phase locked loop type circuit. For example, according to such a feedback signal, a memory controller 902 can delay an enable signal (e.g., output enable OE, write enable WE, address strobe ADS, synchronous read/write R/W, to name but a few).
The above use of timing circuits can be an improvement over previous designs without such feedback, and can account or compensate for variations in delays of enable signals from a memory controller 902. However, it is not wholly satisfactory for a number of reasons.
In particular, current generation memory devices, for example synchronous SRAMs, are not know to have a method or circuit for controlling a DVW when an ambient temperature of the device, either increases or decreases. Thus, feedback loops and the like may not be able to compensate for such variations.
Moreover, as operating frequency of memory devices and systems increases, a DVW can become increasingly more critical. Higher operating speeds result in smaller available time periods for a DVW. Any unwanted reductions, due to PVT variations, may result in an impractically small DVW.
Temperature variations, in particular, may present unwanted changes in a DVW. As is well known, integrated circuit memory devices are formed with transistors. The inherent characteristic of a transistor is to slow down as temperature increases and get faster as it decreases. This can affect the propagation speed of data along a data path of the memory device, and hence timing for the output and input of data to the device. At higher temperatures, a start time of a DVW in relation to a clock can be shifted forward (e.g., occur later in time). Conversely, as temperature decreases and the speed of the memory device increases, there may not be enough output hold time (Tdoh) to enable an external circuit to latch data from the memory device.
One example of dependence of a DVW on an operating temperature of a memory device is illustrated in FIGS. 10A and 10B. FIG. 10A is a timing diagram of a DVW of a conventional memory system. FIG. 10B is a description of the timing diagram of FIG. 10A. The timing values of FIGS. 10A and 10B show the following: a “clock rise to data valid time” Tco and a data output hold time Tdoh.
Variations due to a “hot” temperature include a change in Tco, shown as D_Tco(hot), and a change in Tdoh, shown as D_Tdoh(hot).
Variations due to a “cold” temperature include a change in Tco, shown as D_Tco(cold) and a change in Tdoh, shown as D_Tdoh(cold).
It is understood that the variations due to temperature changes are not necessarily the same for both hot and cold temperatures. That is, D_Tco(hot) will be the same as D_Tco(cold), and D_Tdoh(hot) will be the same as D_Tdoh(cold) only by coincidence.
FIG. 10B illustrates how delays in speed for hot conditions can increase a set-up time and a hold time. Similarly, FIG. 10B shows how increased speed for hot conditions can decrease a set-up time and a hold time.
Accordingly, there is a need for a memory device and/or memory device architecture that includes some mechanism for controlling a DVW such that a DVM for the device can be substantially unaffected by variations in temperature of the device.